555 Timer Calculator
Astable (oscillator) and monostable (one-shot), in both directions: analyse the parts you have, or design from the frequency, duty cycle, or pulse width you want down to resistors you can actually buy. Everything runs in this page — nothing is uploaded.
Astable — what do my parts do?
The standard two-resistor oscillator. The capacitor charges through R1 + R2 and discharges through R2 alone.
Astable — design for a target
Pick the capacitor you have, say what frequency and duty cycle you want, and get the exact R1/R2 plus the nearest standard (E24) values — and what those buyable resistors really produce.
Monostable — one-shot pulse
A trigger starts a single output pulse of ln(3) × R × C (the familiar 1.1 RC), after which the output falls regardless of the input.
Design for a target pulse width
Why the numbers and the bench disagree
The timing equations have no opinion about whether a design is buildable, which is where most 555 projects actually go wrong:
- A standard astable can't do 50% duty or below. Charging goes through R1 + R2, discharging through R2 alone, so high time always exceeds low time. It approaches 50% as R2 grows relative to R1 and never reaches it. A diode across R2 (so charging bypasses R2) buys you 50% and below.
- R1 sets the discharge current. When discharge begins, R1 alone limits current into the discharge pin, which sinks roughly 200 mA at most. This page checks that against your supply voltage.
- Big timing resistors drift. Past about 1 MΩ the threshold pin's own leakage stops being negligible next to the charging current on a bipolar NE555, so the real period wanders — with temperature, and between chips. A CMOS 555 (7555/TLC555) is far more tolerant.
- Electrolytic timing caps are approximate. −20%/+80% is a common tolerance, so a microfarad-scale design's frequency is a target, not a specification. Trim with R2 if it matters.
Common questions
Why can't a 555 astable produce a 50% duty cycle?
In the standard two-resistor astable the timing capacitor charges through R1 + R2 but discharges through R2 alone, so the output-high time is always longer than the output-low time. The duty cycle approaches 50% as R2 grows relative to R1 but never reaches it. To get 50% or below, put a diode across R2 so charging bypasses it, or use a CMOS 555 in a 50%-duty configuration.
What is the 555 astable frequency formula?
The period is ln(2) × (R1 + 2 × R2) × C, which is where the familiar f = 1.44 / ((R1 + 2 × R2) × C) comes from — 1.44 is 1 / ln(2). The output-high time is ln(2) × (R1 + R2) × C and the output-low time is ln(2) × R2 × C.
How long is a 555 monostable pulse?
ln(3) × R × C, usually quoted as the rule of thumb 1.1 × R × C. The capacitor charges from 0 V to the 2/3 Vcc threshold, and ln(3) is the time constant multiple that takes.
How small can R1 be in a 555 astable?
About 1 kΩ in practice. During the discharge phase R1 is the only thing limiting current into the 555's discharge pin, which sinks at most around 200 mA. A smaller R1 satisfies the timing equations but can exceed that rating.